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dual if receiver ad6643 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features performance with nsr enabled snr: 76.1 dbfs in a 40 mhz band to 90 mhz at 185 msps snr: 73.6 dbfs in a 60 mhz band to 90 mhz at 185 msps performance with nsr disabled snr: 66.5 dbfs up to 90 mhz at 185 msps sfdr: 88 dbc up to 185 mhz at 185 msps total power consumption: 706 mw at 200 msps 1.8 v supply voltages lvds (ansi-644 levels) outputs integer 1-to-8 input clock divider (625 mhz maximum input) internal adc voltage reference flexible analog input range 1.4 v p-p to 2.0 v p-p (1.75 v p-p nominal) differential analog inputs with 400 mhz bandwidth 95 db channel isolation/crosstalk serial port control energy saving power-down modes user-configurable, built-in self test (bist) capability applications communications diversity radio and smart antenna (mimo) systems multimode digital receivers (3g) wcdma, lte, cdma2000 wimax, td-scdma i/q demodulation systems general-purpose software radios general description the ad6643 is an 11-bit, 200 msps, dual-channel intermediate frequency (if) receiver specifically designed to support multi- antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. the device consists of two high performance analog-to-digital converters (adcs) and noise shaping requantizer (nsr) digital blocks. each adc consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each adc features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. an integrated voltage reference eases design considerations. a duty cycle stabilizer (dcs) compensates for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. functional block diagram vin+a d0 d10 vin?a pipeline adc noise shaping requantizer vin+b vin?b notes 1. the d0 to d10 pins represent both the channel a and channel b lvds output data. pipeline adc serial port reference 14 11 noise shaping requantizer ad6643 data multiplexer and lvds drivers 14 11 clock divider vcm dco oeb sclk sdio csb clk+ a vdd agnd drvdd clk? sync pdwn 09638-001 figure 1. each adc output is connected internally to an nsr block. the integrated nsr circuitry allows for improved snr performance in a smaller frequency band within the nyquist bandwidth. the device supports two different output modes selectable via the spi. with the nsr feature enabled, the outputs of the adcs are processed such that the ad6643 supports enhanced snr per- formance within a limited portion of the nyquist bandwidth while maintaining an 11-bit output resolution. the nsr block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. for example, with a sample clock rate of 185 msps, the ad6643 can achieve up to 75.5 dbfs snr for a 40 mhz bandwidth in the 22% mode and up to 73.7 dbfs snr for a 60 mhz bandwidth in the 33% mode. (continued on page 3)
ad6643 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 product highlights ........................................................................... 3 specifications..................................................................................... 4 adc dc specifications................................................................. 4 adc ac specifications ................................................................. 5 digital specifications ..................................................................... 6 switching specifications ................................................................ 8 timing specifications .................................................................. 8 absolute maximum ratings.......................................................... 10 thermal characteristics ............................................................ 10 esd caution................................................................................ 10 pin configurations and function descriptions ......................... 11 typical performance characteristics ........................................... 15 equivalent circuits ......................................................................... 18 theory of operation ...................................................................... 19 adc architecture ...................................................................... 19 analog input considerations.................................................... 19 voltage reference ....................................................................... 21 clock input considerations...................................................... 21 power dissipation and standby mode .................................... 22 digital outputs ........................................................................... 23 noise shaping requantizer (nsr) ............................................... 24 22% bw mode (>40 mhz at 184.32 msps)........................... 24 33% bw mode (>60 mhz at 184.32 msps)........................... 25 channel/chip synchronization.................................................... 26 serial port interface (spi).............................................................. 27 configuration using the spi..................................................... 27 hardware interface..................................................................... 27 spi accessible features.............................................................. 28 memory map .................................................................................. 29 reading the memory map register table............................... 29 memory map register table..................................................... 30 memory map register description ......................................... 32 applications information .............................................................. 34 design guidelines ...................................................................... 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 4/11revision 0: initial version
ad6643 rev. 0 | page 3 of 36 when the nsr block is disabled, the adc data is provided directly to the output at a resolution of 11 bits. the ad6643 can achieve up to 66.5 dbfs snr for the entire nyquist bandwidth when operated in this mode. this allows the ad6643 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required. after digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 mbps (ddr). these outputs are lvds and support ansi-644 levels. the ad6643 receiver digitizes a wide spectrum of if frequencies. each receiver is designed for simultaneous reception of a separate antenna. this if sampling architecture greatly reduces compo- nent cost and complexity compared with traditional analog techniques or less integrated digital methods. flexible power-down options allow significant power savings. programming for device setup and control is accomplished using a 3-wire spi-compatible serial interface with numerous modes to support board level system testing. the ad6643 is available in a pb-free, rohs compliant, 64-lead, 9 mm 9 mm lead frame chip scale package (lfcsp_vq) and is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. product highlights 1. two adcs are contained in a small, space-saving, 9 mm 9 mm 0.85 mm, 64-lead lfcsp package. 2. pin selectable noise shaping requantizer (nsr) function that allows for improved snr within a reduced bandwidth of up to 60 mhz at 185 msps. 3. lvds digital output interface configured for low cost fpga families. 4. operation from a single 1.8 v supply. 5. standard serial port interface (spi) that supports various product features and functions, such as data formatting (offset binary or twos complement), nsr, power-down, test modes, and voltage reference mode. 6. on-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.
ad6643 rev. 0 | page 4 of 36 specifications adc dc specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.75 v p-p full-scale input range, defaul t spi, unless otherwise noted. table 1. parameter temperature min typ max unit resolution full 11 bits accuracy no missing codes full guaranteed offset error full 10 mv gain error full +2/?6 % fsr differential nonlinearity (dnl) 1 full 0.1 0.25 lsb integral nonlinearity (inl) 1 full 0.2 0.25 lsb matching characteristic offset error 25c 13 mv gain error 25c ?2/+3.5 % fsr temperature drift offset error full 15 ppm/c gain error full 50 ppm/c input referred noise vref = 1.0 v 25c 0.614 lsb rms analog input input span full 1.75 v p-p input capacitance 2 full 2.5 pf input resistance 3 full 20 k input common-mode voltage full 0.9 v power supplies supply voltage avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v supply current i avdd 1 full 238 260 ma i drvdd 1 full 154 215 ma power consumption sine wave input 1 (drvdd = 1.8 v) full 706 855 mw standby power 4 full 90 mw power-down power full 10 mw 1 measured using a 10 mhz, 0 dbfs sine wave, and 100 terminatio n on each lvds output pair. 2 input capacitance refers to the effective capacitanc e between one differential input pin and its complement. 3 input resistance refers to the effective resistance between one differential input pin and its complement. 4 standby power is measured using a dc input and the clk pins inactive (set to avdd or agnd).
ad6643 rev. 0 | page 5 of 36 adc ac specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.75 v p-p full-scale input range, defaul t spi, unless otherwise noted. table 2. parameter 1 temperature min typ max unit signal-to-noise-ratio (snr) nsr disabled f in = 30 mhz 25c 66.6 dbfs f in = 90 mhz 25c 66.5 dbfs full 66.2 dbfs f in = 140 mhz 25c 66.4 dbfs f in = 185 mhz 25c 66.2 dbfs f in = 220 mhz 25c 66.0 dbfs nsr enabled 22% bw mode f in = 90 mhz 25c 76.1 dbfs f in = 140 mhz 25c 75.5 dbfs f in = 185 mhz 25c 74.7 dbfs f in = 220 mhz 25c 74.2 dbfs 33% bw mode f in = 90 mhz 25c 73.6 dbfs f in = 140 mhz 25c 73.1 dbfs f in = 185 mhz 25c 72.6 dbfs f in = 220 mhz 25c 72.1 dbfs signal-to-noise-and-distortion (sinad) f in = 30 mhz 25c 65.6 dbfs f in = 90 mhz 25c 65.5 dbfs full 65.1 dbfs f in = 140 mhz 25c 65.3 dbfs f in = 185 mhz 25c 65.1 dbfs f in = 220 mhz 25c 64.9 dbfs worst second or third harmonic f in = 30 mhz 25c ?92 dbc f in = 90 mhz 25c ?91 dbc full ?80 dbc f in = 140 mhz 25c ?88 dbc f in = 185 mhz 25c ?88 dbc f in = 220 mhz 25c ?84 dbc spurious-free dynamic range (sfdr) f in = 30 mhz 25c 92 dbc f in = 90 mhz 25c 91 dbc full 80 dbc f in = 140 mhz 25c 88 dbc f in = 185 mhz 25c 88 dbc f in = 220 mhz 25c 84 dbc worst other harmonic or spur f in = 30 mhz 25c ?94 dbc f in = 90 mhz 25c ?94 dbc full ?80 dbc f in = 140 mhz 25c ?95 dbc f in = 185 mhz 25c ?94 dbc f in = 220 mhz 25c ?93 dbc
ad6643 rev. 0 | page 6 of 36 parameter 1 temperature min typ max unit two tone sfdr f in = 184.12 mhz, 187.12 mhz (?7 dbfs) 25c 88 dbc crosstalk 2 full 95 db full power bandwidth 3 25c 400 mhz noise bandwidth 4 25c 1000 mhz 1 for a complete set of definitions, see the an-835 application note, understanding high speed adc testing and evaluation . 2 crosstalk is measured at 100 mhz with ?1 dbfs on on e channel and with no input on the alternate channel. 3 full power bandwidth is the bandwidth of operation where typical adc performance can be achieved. 4 noise bandwidth is the ?3 db bandwidth for the adc inputs across which noise may enter the adc and it is not attenuated intern ally. digital specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.75 v p-p full-scale input range, dcs enabled, default spi, unless otherwise noted. table 3. parameter temperature min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common-mode bias full 0.9 v differential input voltage full 0.3 3.6 v p-p input voltage range full agnd avdd v input common-mode range full 0.9 1.4 v input current level high full 10 22 a low full ?22 ?10 a input capacitance full 4 pf input resistance full 8 10 12 k sync input logic compliance cmos/lvds internal bias full 0.9 v input voltage range full agnd avdd v input voltage level high full 1.2 avdd v low full agnd 0.6 v input current level high full ?5 +5 a low full ?100 +100 a input capacitance full 1 pf input resistance full 12 16 20 k logic input (csb) 1 input voltage level high full 1.22 2.1 v low full 0 0.6 v input current level high full ?5 +5 a low full ?80 ?45 a input resistance full 26 k input capacitance full 2 pf logic input (sclk) 2 input voltage level high full 1.22 2.1 v low full 0 0.6 v
ad6643 rev. 0 | page 7 of 36 parameter temperature min typ max unit input current level high full 45 70 a low full ?5 +5 a input resistance full 26 k input capacitance full 2 pf logic inputs (sdio) 1 input voltage level high full 1.22 2.1 v low full 0 0.6 v input current level high full 45 70 a low full ?5 +5 a input resistance full 26 k input capacitance full 5 pf logic inputs (oeb, pdwn) 2 input voltage level high full 1.22 2.1 v low full 0 0.6 v input current level high full 45 70 a low full ?5 +5 a input resistance full 26 k input capacitance full 5 pf digital outputs lvds data and or outputs differential output voltage (vod) ansi mode full 250 350 450 mv reduced swing mode full 150 200 280 mv output offset voltage (vos) ansi mode full 1.15 1.25 1.35 v reduced swing mode full 1.15 1.25 1.35 v 1 pull up. 2 pull down.
ad6643 rev. 0 | page 8 of 36 switching specifications table 4. parameter symbol temperature min typ max unit clock input parameters input clock rate full 625 mhz conversion rate 1 full 40 200 msps clk perioddivide-by-1 mode 2 t clk full 4.0 ns clk pulse width high 2 t ch divide-by-1 mode, dcs enabled full 2.25 2.5 2.75 ns divide-by-1 mode, dcs disabled full 2.375 2.5 2.625 ns divide-by-2 through divide-by-8 modes, dcs enabled full 0.8 ns data output parameters (data, or) lvds mode data propagation delay 2 t pd full 4.8 ns dco propagation delay 2 t dco full 5.5 ns dco to data skew 2 t skew full 0.1 0.7 1.3 ns pipeline delay (latency) full 10 cycles 3 nsr enabled full 13 cycles 3 aperture delay 4 t a full 1.0 ns aperture uncertainty (jitter) 4 t j full 0.1 ps rms wake-up time (from standby) full 10 s wake-up time (from power-down) full 250 s out-of-range recovery time full 3 cycles 1 conversion rate is the clock rate after the divider. 2 see for timing diagram. figure 2 3 cycles refers to adc input sample rate cycles. 4 not shown in timing diagrams. timing specifications table 5. parameter conditions min typ max unit sync timing requirements see figure 3 for timing details t ssync sync to the rising edge of clk setup time 0.3 ns t hsync sync to the rising edge of clk hold time 0.4 ns spi timing requirements see figure 45 for spi timing diagram t ds setup time between the data and th e rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high minimum period that sclk should be in a logic high state 10 ns t low minimum period that sclk should be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 45 ) 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 45 ) 10 ns
ad6643 rev. 0 | page 9 of 36 timing diagrams vin clk+ clk? dco? dco+ d0 (lsb) parallel interleaved channel multiplexed (even/odd) mode channel multiplexed (even/odd) mode d11 (msb) 0/d0 (lsb) ch a n ? 10 ch b n ? 10 ch a n ? 9 ch b n ? 9 ch a n ? 8 ch b n ? 8 ch a n ? 7 ch b n ? 7 ch a n ? 6 ch a n ? 10 ch b n ? 10 ch a n ? 9 ch b n ? 9 ch a n ? 8 ch b n ? 8 ch a n ? 7 ch b n ? 7 ch a n ? 6 ch a0 n ? 10 ch a1 n ? 10 ch a0 n ? 9 ch a1 n ? 9 ch a0 n ? 8 ch a1 n ? 8 ch a0 n ? 7 ch a1 n ? 7 ch a0 n ? 6 ch a10 n ? 10 ch a11 n ? 10 ch a10 n ? 9 ch a11 n ? 9 ch a10 n ? 8 ch a11 n ? 8 ch a10 n ? 7 ch a11 n ? 7 ch a10 n ? 6 ch b0 n ? 10 ch b1 n ? 10 ch b0 n ? 9 ch b1 n ? 9 ch b0 n ? 8 ch b1 n ? 8 ch b0 n ? 7 ch b1 n ? 7 ch b0 n ? 6 ch b10 n ? 10 ch b11 n ? 10 ch b10 n ? 9 ch b11 n ? 9 ch b10 n ? 8 ch b11 n ? 8 ch b10 n ? 7 ch b11 n ? 7 ch b10 n ? 6 channel a d9/d10 (msb) 0/d0 (lsb) channel b d9/d10 (msb) n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 t a t ch t pd t skew t dco t clk 09638-002 . . . . . . . . . channel a and channel b figure 2. lvds modes for data output timing latency , nsr disabled (enabling nsr adds an a dditional three clock cycles of latenc y) t ssync t hsync sync clk+ 09638-003 figure 3. sync timing inputs
ad6643 rev. 0 | page 10 of 36 absolute maximum ratings table 6. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0 v vin+a/vin+b, vin?a/vin?b to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v sync to agnd ?0.3 v to avdd + 0.2 v vcm to agnd ?0.3 v to avdd + 0.2 v csb to agnd ?0.3 v to drvdd + 0.3 v sclk to agnd ?0.3 v to drvdd + 0.3 v sdio to agnd ?0.3 v to drvdd + 0.3 v oeb to agnd ?0.3 v to drvdd + 0.3 v pdwn to agnd ?0.3 v to drvdd + 0.3 v or+/or? to agnd ?0.3 v to drvdd + 0.3 v d0?/d0+ through d10?/d10+ to agnd ?0.3 v to drvdd + 0.3 v dco+/dco? to agnd ?0.3 v to drvdd + 0.3 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ?65c to +125c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the printed circuit board (pcb) increases the re liability of the solder joints, maximizing the thermal capability of the package. typical ja is specified for a 4-layer pcb that uses a solid ground plane. as listed in table 7 , airflow increases heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the ja . table 7. thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 unit 0 26.8 1.14 10.4 c/w 1.0 21.6 c/w 64-lead lfcsp 9 mm 9 mm (cp-64-4) 2.0 20.2 c/w 1 per jedec 51-7, plus jede c 25-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per mil-std 883, method 1012.1. 4 per jedec jesd51-8 (still air). esd caution
ad6643 rev. 0 | page 11 of 36 pin configurations and function descriptions 09638-004 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d1? d1+ drvdd d2? d2+ d3? d3+ dco? dco+ d4? d4+ drvdd d5? d5+ d6? d6+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd avdd vin+b vin?b avdd avdd dnc vcm dnc dnc avdd avdd vin?a vin+ a avdd avdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk+ clk? sync dnc dnc dnc dnc dnc dnc drvdd dnc dnc dnc dnc d0? (lsb) d0+ (lsb) notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. pdwn oeb csb sclk sdio or+ or? d10+ (msb) d10? (msb) d9+ d9? drvdd d8+ d8? d7+ d7? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad6643 interleaved parallel lvds top view (not to scale) pin 1 indicator figure 4. pin configuration (top view), lfcsp interleaved parallel lvds table 8. pin function descriptions fo r the interleaved parallel lvds mode pin no. mnemonic type description adc power supplies 10, 19, 28, 37 drvdd supply digital o utput driver supply (1.8 v nominal). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 4 to 9, 11 to 14, 55, 56, 58 dnc do not connect. do not connect to these pins. 0 agnd, exposed paddle ground analog ground. the exposed thermal paddle on the bottom of the package provides the analog ground for the device. this exposed paddle must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin?a input differential analog input pin (?) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin?b input differential analog input pin (?) for channel b. 57 vcm output common-mode level bias output for analog inputs. this pin should be decoupled to ground using a 0.1 f capacitor. 1 clk+ input adc clock inputtrue. 2 clk? input adc clock inputcomplement. digital input 3 sync input digital synchronization pin. slave mode only. digital outputs 15 d0? (lsb) output channel a/channel b lvds output data 0true. 16 d0+ (lsb) output channel a/channel b lvds output data 0complement. 18 d1+ output channel a/channel b lvds output data 1true. 17 d1? output channel a/channel b lvds output data 1complement. 21 d2+ output channel a/channel b lvds output data 2true. 20 d2? output channel a/channel b lvds output data 2complement. 23 d3+ output channel a/channel b lvds output data 3true. 22 d3? output channel a/channel b lvds output data 3complement.
ad6643 rev. 0 | page 12 of 36 pin no. mnemonic type description 27 d4+ output channel a/channel b lvds output data 4true. 26 d4? output channel a/channel b lvds output data 4complement. 30 d5+ output channel a/channel b lvds output data 5true. 29 d5? output channel a/channel b lvds output data 5complement. 32 d6+ output channel a/channel b lvds output data 6true. 31 d6? output channel a/channel b lvds output data 6complement. 34 d7+ output channel a/channel b lvds output data 7true. 33 d7? output channel a/channel b lvds output data 7complement. 36 d8+ output channel a/channel b lvds output data 8true. 35 d8? output channel a/channel b lvds output data 8complement. 39 d9+ output channel a/channel b lvds output data 9true. 38 d9? output channel a/channel b lvds output data 9complement. 41 d10+ (msb) output channel a/channel b lvds output data 10true. 40 d10? (msb) output channel a/channe l b lvds output data 10complement. 43 or+ output channel a/channe l b lvds overrangetrue. 42 or? output channel a/channel b lvds overrangecomplement. 25 dco+ output channel a/channel b lvds data clock outputtrue. 24 dco? output channel a/channel b lv ds data clock outputcomplement. spi control 45 sclk input spi serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. 44 sdio input/output spi serial data i/o. a dual purpose pin that typically serves as an input or an output, depending on the instru ction being sent and the relative position in the timing frame. 46 csb input chip select bar (active low). csb gates the read and write cycles. output enable and power-down 47 oeb input/output output enable input (active low). 48 pdwn input/output power-down input (active high). the operation of this pin depends on the spi mode and can be configured as power-down or standby (see table 14 ).
ad6643 rev. 0 | page 13 of 36 09638-005 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 b d5?/d6? b d5+/d6+ drvdd b d7?/d8? b d7+/d8+ b d9?/d10? (msb) b d9+/d10+ (msb) dco? dco+ dnc dnc drvdd a 0/d0? (lsb) a 0/d0+ (lsb) a d1?/d2? a d1+/d2+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd avdd vin+b vin?b avdd avdd dnc vcm dnc dnc avdd avdd vin?a vin+a avdd avdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk+ clk? sync dnc dnc dnc dnc dnc dnc drvdd b0/d0?(lsb) b0/d0+(lsb) bd1?/d2? bd1+/d2+ bd3?/d4? bd3+/d4+ notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. pdwn oeb csb sclk sdio or+ or? ad9+/d10+(msb) a d9?/d10? (msb) ad7+/d8+ a d7?/d8? drvdd ad5+/d6+ a d5?/d6? ad3+/d4+ a d3?/d4? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad6643 channel multiplexed (even/odd) lvds mode top view (not to scale) pin 1 indicator figure 5. pin configuration (top view), lfcsp channel multiplexed (even/odd) lvds table 9. pin function descriptions for the channel multiplexed (even/odd) lvds mode pin no. mnemonic type description adc power supplies 10, 19, 28, 37 drvdd supply digital o utput driver supply (1.8 v nominal). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 4 to 9, 26, 27, 55, 56, 58 dnc do not connect. do not connect to these pins. 0 agnd, exposed paddle ground the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin?a input differential analog input pin (?) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin?b input differential analog input pin (?) for channel b. 57 vcm output common-mode level bias output for analog inputs. this pin should be decoupled to ground using a 0.1 f capacitor. 1 clk+ input adc clock inputtrue. 2 clk? input adc clock inputcomplement. digital input 3 sync input digital synchronization pin. slave mode only. digital outputs 11 b 0/d0? (lsb) output channel b lvds output 0/data 0comple ment. the output bit on the rising edge of the data clock output (dco) fr om this output is always a logic 0. 12 b 0/d0+ (lsb) output channel b lvds output 0/data 0true. the output bit on the rising edge of the data clock output (dco) from th is output is always a logic 0. 13 b d1?/d2? output channel b lvds output data 1/data 2complement. 14 b d1+/d2+ output channel b lvds output data 1/data 2true. 15 b d3?/d4? output channel b lvds output data 3/data 4complement.
ad6643 rev. 0 | page 14 of 36 pin no. mnemonic type description 16 b d3+/d4+ output channel b lvds output data 3/data 4true. 17 b d5?/d6? output channel b lvds output data 5/data 6complement. 18 b d5+/d6+ output channel b lvds output data 5/data 6true. 20 b d7?/d8? ouput channel b lvds output data 7/data 8complement. 21 b d7+/d8+ output channel b lvds output data 7/data 8true. 22 b d9?/d10? (msb) output channel b lvds output data 9/data 10complement. 23 b d9+/d10+ (msb) output channel b lvds output data 9/data 10true. 29 a 0/d0? (lsb) output channel b lvds output 0/data 1compleme nt. the first output bit from this output is always a logic 0. 30 a 0/d0+ (lsb) output channel b lvds output 0/data 1true. th e first output bit fr om this output is always a logic 0. 31 a d1?/d2? output channel a lvds output data 1/data 0complement. 32 a d1+/d2+ output channel a lvds output data 1/data 0true. 33 a d3?/d4? output channel a lvds output data 3/data 2complement. 34 a d3+/d4+ output channel a lvds output data 3/data 2true. 35 a d5?/d6? output channel a lvds output data 5/data 4complement. 36 a d5+/d6+ output channel a lvds output data 5/data 4true. 38 a d7?/d8? output channel a lvds output data 7/data 6complement. 39 a d7+/d8+ output channel a lvds output data 7/data 6true. 40 a d9?/d10? (msb) output channel a lv ds output data 9/data 8complement. 41 a d9+/d10+ (msb) output channel a lvds output data 9/data 8true. 43 or+ output channel a/channel b lvds overrange outputtrue. 42 or? output channel a/channel b lvds overrange outputcomplement. 25 dco+ output channel a/channel b lvds data clock outputtrue. 24 dco? output channel a/channel b lv ds data clock outputcomplement. spi control 45 sclk input spi serial clock (sckl). the serial shift clock input, which is used to synchronize serial interface reads and writes. 44 sdio input/output spi serial data input/output (sdio). a dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. 46 csb input spi chip select bar (active low). an active low control that gates the read and write cycles. adc configuration 47 oeb input output enable input (active low). 48 pdwn input power-down input (active high). the operation of this pin depends on the spi mode and can be configured as power-down or standby (see table 14 ).
ad6643 rev. 0 | page 15 of 36 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, sample rate = 200 msps, dcs enabled, 1.75 v p-p differential input, vin = ?1.0 dbfs, 32k sample, t a = 25c, unless otherwise noted. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100 frequency (mhz) amplitude (dbfs) 09638-006 200msps 30.1mhz @ ?1dbfs snr = 65.8db (66.8dbfs) sfdr = 88dbc figure 6. single tone fft, f in = 30.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100 frequency (mhz) amplitude (dbfs) 09638-007 200msps 90.1mhz @ ?1dbfs snr = 65.5db (66.5dbfs) sfdr = 88dbc figure 7. single tone fft, f in = 90.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100 frequency (mhz) amplitude (dbfs) 09638-008 200msps 140.1mhz @ ?1dbfs snr = 65.4db (66.4dbfs) sfdr = 87.5dbc third harmonic figure 8. single tone fft, f in = 140.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100 frequency (mhz) amplitude (dbfs) 09638-009 200msps 185.1mhz @ ?1dbfs snr = 65.2db (66.2dbfs) sfdr = 87.5dbc third harmonic figure 9. single tone fft, f in = 185.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100 frequency (mhz) amplitude (dbfs) 09638-010 200msps 220.1mhz @ ?1dbfs snr = 65db (66dbfs) sfdr = 84dbc third harmonic second harmonic figure 10. single tone fft, f in = 220.1 mhz 0 ?20 third harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100 frequency (mhz) amplitude (dbfs) 09638-011 200msps 305.1mhz @ ?1dbfs snr = 64.4db (65.4dbfs) sfdr = 79dbc figure 11. single tone fft, f in = 305.1 mhz
ad6643 rev. 0 | page 16 of 36 120 100 80 60 40 20 0 ?10 ?20 ?30?40?50?60?70?80?90?100 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09638-012 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) figure 12. single tone snr/ sfdr vs. input amplitude (a in ), f in = 90.1 mhz 100 95 90 85 80 75 70 65 60 195 185 175 145 155 165 13512511510595857565 frequency (mhz) snr/sfdr (dbc and dbfs) 09638-013 snr (dbfs) sfdr (dbc) figure 13. single tone snr/ sfdr vs. input frequency (f in ) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09638-014 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 14. two tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 89.12 mhz, f in2 = 92.12 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09638-015 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 15. two tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184.12 mhz, f in2 = 187.12 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100 frequency (mhz) amplitude (dbfs) 09638-016 200msps 89.12mhz @ ?7dbfs 92.12mhz @ ?7dbfs sfdr = 89dbc (96dbfs) figure 16. two tone fft with f in1 = 89.12 mhz, f in2 = 92.12 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100 frequency (mhz) amplitude (dbfs) 09638-017 200msps 184.12mhz @ ?7dbfs 187.12mhz @ ?7dbfs sfdr = 86dbc (93dbfs) figure 17. two tone fft with f in1 = 184.12 mhz, f in2 = 187.12 mhz
ad6643 rev. 0 | page 17 of 36 100 95 90 85 80 75 70 65 60 130 140 150 160 120110100908070605040 170 180 190 200 sample rate (msps) snr/sfdr (dbc and dbfs) 09638-018 snr, channel b sfdr, channel b snr, channel a sfdr, channel a figure 18. single tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 12,000 10,000 8000 6000 4000 2000 0 n + 1 n output code number of hits 09638-019 0.614lsb rms 16,384 total hits figure 19. grounded input histogram
ad6643 rev. 0 | page 18 of 36 equivalent circuits v in avdd 09638-027 figure 20. equivalent analog input circuit 0.9v 15k ? 15k? c lk+ clk? avdd 09638-028 avdd avdd figure 21. equivalent clock lnput circuit 0 9638-053 d r v dd dataout+ v? v+ dataout? v+ v? figure 22. equivalent lvds output circuit sdio 350? 26k ? drvdd 09638-030 figure 23. equivalent sdio circuit sclk or pdwn 350 ? 26k ? 09638-031 figure 24. equivalent sclk or pdwn input circuit csb or o eb 350 ? 26k ? a vdd 09638-032 figure 25. equivalent cs b or oeb input circuit avdd avdd 16k? 0.9v 0.9v sync 0 9638-033 figure 26. equivalent sync input circuit
ad6643 rev. 0 | page 19 of 36 theory of operation the ad6643 has two analog input channels and two digital output channels. the intermediate frequency (if) input signal passes through several stages before appearing at the output port(s) as a filtered, and optionally decimated, digital signal. adc architecture the ad6643 architecture consists of dual front-end sample- and-hold circuits, followed by pipelined, switched capacitor adcs. the quantized outputs from each stage are combined into a final 11-bit result in the digital correction logic. alternately, the 11-bit result can be processed through the noise shaping requantizer (nsr) block before it is sent to the digital correc- tion logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor digital- to-analog converter (dac) and an interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the out- put drive current. during power-down, the output buffers enter a high impedance state. the ad6643 dual if receiver can simultaneously digitize two channels, making it ideal for diversity reception and digital pre- distortion (dpd) observation paths in telecommunication systems. the dual if receiver design can be used for diversity reception of signals, whereas the adcs operate identically on the same carrier but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can input frequencies from dc to 300 mhz using appropriate low-pass or band-pass filtering at the adc inputs with little loss in performance. operation to 400 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. synchronization capability is provided to allow synchronized timing between multiple devices. programming and control of the ad6643 are accomplished using a 3-wire spi-compatible serial interface. analog input considerations the analog input to the ad6643 is a differential switched capacitor circuit designed for optimum performance in differential signal processing. the clock signal alternatively switches the input between sample mode and hold mode (see figure 27 ). when the input is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, any shunt capacitors placed across the inputs should be reduced. in combination with the driving source impedance, the shunt capa- citors limit the input bandwidth. for more information, refer to the an-742 application note, frequency domain response of switched-capacitor adcs ; the an-827 application note, a resonant approach to interfacing amplifiers to switched-capacitor adcs ; and the analog dialogue article, transformer-coupled front-end for wideband a/d converters, available at www.analog.com . c par1 c par1 c par2 c par2 s s s s s s c fb c fb c s c s bias bias v in+ 09638-034 h v in? figure 27. switched capacitor input for best dynamic performance, match the source impedances driving vin+ and vin? and differentially balance the inputs. input common mode the analog inputs of the ad6643 are not internally dc biased. in ac-coupled applications, the user must provide this bias exter- nally. setting the device so that v cm = 0.5 avdd (or 0.9 v) is recommended for optimum performance. an on-board common-mode voltage reference is included in the design and is available from the vcm pin. using the vcm output to set the input common mode is recommended. optimum perfor- mance is achieved when the common-mode voltage of the analog input is set by the vcm pin voltage (typically 0.5 avdd). the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. place this
ad6643 rev. 0 | page 20 of 36 decoupling capacitor close to the vcm pin to minimize series resistance and inductance between the device and this capacitor. differential input configurations optimum performance is achieved by driving the ad6643 in a differential input configuration. for baseband applications, the ad8138 , ada4937-2 , ada4930-2 , and ada4938-2 differential drivers provide excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad a4938-2 is easily set with the vcm pin of the ad6643 (see figure 28 ), and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. 76.8 ? 120 ? 0.1f 0.1f 200? 200 ? 90? v in avdd 33 ? 33 ? 33? 15 ? 15 ? 5pf 15p f 15pf adc vin? vin+ vcm ada4930-2 09638-035 figure 28. differential input configuration using the ada4930-2 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration, as shown in figure 29 . to bias the analog input, the vcm voltage can be connected to the center tap of the secondary winding of the transformer. 2v p-p 49.9 ? 0.1f r1 r1 c1 adc vin+ vin? vcm c2 r2 r3 r2 c2 09638-036 r3 0.1f 33? figure 29. differential transformer-coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz (mhz). excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the ad6643. for applications where snr is a key parameter, differential double balun coupling is the recommended input configuration (see figure 30 ). in this configuration, the input is ac-coupled, and the cml is provided to each input through a 33 resistor. these resistors compensate for losses in the input baluns to provide a 50 impedance to the driver. in the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input fre- quency and source impedance. based on these parameters the value of the input resistors and capacitors may need to be adjusted, or some components may need to be removed. table 10 lists recommended values to set the rc network for different input frequency ranges. however, because these values are dependent on the input signal and bandwidth, they are to be used as a starting guide only. note that the values given in table 10 are for each r1, r2, c2, and r3 component shown in figure 29 and figure 30 . table 10. example rc network freuency range (m) r1 series () c1 differential (pf) r2 series () c2 shunt (pf) r3 shunt () 0 to 100 33 8.2 0 15 49.9 100 to 300 15 3.9 0 8.2 49.9 an alternative to using a transformer-coupled input at frequencies in the second nyquist zone is to use an amplifier with variable gain. the ad8375 or ad8376 digital variable gain amplifiers (dvgas) provide good performance for driving the ad6643. figure 31 shows an example of the ad8376 driving the ad6643 through a band-pass antialiasing filter. adc r1 0.1f 0.1f 2 v p- p vin+ vin? vcm c1 c2 r1 r2 r2 0.1f s 0.1f c2 33? 33? s p a p 09638-037 r3 r3 0.1f 33? figure 30. differential double balun input configuration
ad6643 rev. 0 | page 21 of 36 ad8376 ad6643 1h 1h 1nf 1nf vpos vcm 15pf 68nh 2.5k ?U 2pf 301 ? 165? 165? 5.1pf 3.9pf 1000pf 1000pf notes 1. all inductors are coilcraft 0603cs components with the exception of the 1h choke inductors (0603ls). 2. filter values shown are for a 20mhz bandwidth filter centered at 140mhz. 180nh 220nh 180nh 220nh 09638-038 figure 31. differential input configuration using the ad8376 voltage reference a stable and accurate voltage reference is built into the ad6643. the full-scale input range can be adjusted by varying the reference voltage via the spi. the input span of the adc tracks reference voltage changes linearly. clock input considerations for optimum performance, clock the ad6643 sample clock inputs (clk+ and clk?) by using a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally (see figure 32) and require no external bias. if the inputs are floated, the clk? pin is pulled low to prevent spurious clocking. 0 9638-039 avdd clk+ 4pf 4pf clk? 0.9v figure 32. equivalent clock input circuit clock input options the ad6643 has a very flexible clock input structure. clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 33 and figure 34 show two preferred methods for clocking the ad6643 (at clock rates of up to 625 mhz). a low jitter clock source is converted from a single-ended signal to a differential signal using an rf balun or rf transformer. the rf balun configuration is recommended for clock frequencies between 125 mhz and 625 mhz, and the rf transformer is recom- mended for clock frequencies from 10 mhz to 200 mhz. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the ad6643 to approximately 0.8 v p-p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad6643, yet preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 390pf 390pf 390pf schottky diodes: hsms2822 clock input 50? 100 ? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1z xfmr 0 9638-040 figure 33. transformer-coupled differential clock (up to 200 mhz) 390pf 390pf 390pf clock input 25? 25? clk? clk+ schottky diodes: hsms2822 adc 09638-041 figure 34. balun-coupled differential clock (up to 625 mhz) if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 35. the ad9510, ad9511, ad9512, ad9513, ad9514 , ad9515 , ad9516 , ad9517 , ad9518, ad9520 , ad9522, and the adclk905/adclk907/adclk925 , clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? pecl driver 50k ? 50k ? clk? clk+ clock input clock input ad95xx adc 09638-042 figure 35. differential pecl sample clock (up to 625 mhz) a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 36. the ad9510 , ad9511, ad9512 , ad9513, ad9514, ad9515 , ad9516, ad9517, ad9518 , ad9520, ad9522, ad9523 , and ad9524 clock drivers offer excellent jitter performance.
ad6643 rev. 0 | page 22 of 36 0.1f 0.1f 0.1f 0.1f 100 ? pecl driver 50k ? 50k ? clk? clk+ clock input clock input ad95xx adc 09638-043 figure 36. differential lvds sample clock (up to 625 mhz) input clock divider the ad6643 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. the duty cycle stabilizer (dcs) is enabled by default on power-up. the ad6643 clock divider can be synchronized using the external sync input. bit 1 and bit 2 of register 0x3a allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchro- nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad6643 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, thereby providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the ad6643. jitter on the rising edge of the input clock is of paramount concern and is not reduced by the duty cycle stabilizer. the duty cycle control loop does not function for clock rates of less than 40 mhz nominally. the loop has a time constant associated with it that must be considered when the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time period that the loop is not locked, the dcs loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the dcs. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter (t j ) can be calculated by snr hf = ?10 log[(2 f in t jrms ) 2 + 10 ] )10/( lf snr ? in the equation, the rms aperture jitter represents the root mean square of all jitter sources, which include the clock input, the analog input signal, and the adc aperture jitter specification. if undersampling applications are particularly sensitive to jitter, as shown in figure 37 . 80 75 70 65 60 55 50 1 10 100 1k input frequency (mhz) snr (dbc) 0 9638-044 0.05ps 0.20ps 0.50ps 1.00ps 1.50ps measured figure 37. snr vs. input frequency and jitter in cases where aperture jitter may affect the dynamic range of the ad6643, treat the clock input as an analog signal. separate power supplies for clock drivers from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. refer to the an-501 application note, aperture uncertainty and adc system performance , and the an-756 application note, sample systems and the effects of clock phase noise and jitter , for more information about jitter performance as it relates to adcs (see www.analog.com ). power dissipation and standby mode as shown in figure 38 , the power dissipated by the ad6643 is proportional to its sample rate. the data in figure 38 was taken using the same operating conditions as those used for the typical performance characteristics . 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.25 0.20 0.15 0.10 0.05 0 0 40 60 80 100 120 140 160 180 200 encode frequency (msps) total power (w) supply current (a) 09638-045 total power i avdd i drvdd figure 38. ad6643 power and current vs. sample rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the ad6643 is placed in power-down mode. in this state, the adc typically dissipates 10 mw. during
ad6643 rev. 0 | page 23 of 36 power-down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad6643 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power- down mode and then must be recharged when returning to normal operation. as a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. when using the spi port interface, the user can place the adc in power-down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. see the memory map register description section and the an-877 application note, interfacing to high speed adcs via spi, available at www.analog.com for additional details. digital outputs the ad6643 output drivers can be configured for either ansi lvds or reduced drive lvds using a 1.8 v drvdd supply. as detailed in the an-877 application note, interfacing to high speed adcs via spi , the data format can be selected for offset binary, twos complement, or gray code when using the spi control. digital output enable function (oeb) the ad6643 has a flexible three-state ability for the digital output pins. the three-state mode is enabled using the oeb pin or through the spi interface. if the oeb pin is low, the output data drivers are enabled. if the oeb pin is high, the output data drivers are placed in a high impedance state. this oeb function is not intended for rapid access to the data bus. note that oeb is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. when using the spi interface, the data outputs of each channel can be independently three-stated by using the output disable bar bit (bit 4) in register 0x14. because the output data is inter- leaved, if only one of the two channels is disabled, the data from the remaining channel is repeated in both the rising and falling output clock cycles. timing the ad6643 provides latched data with a pipeline delay of 10 input sample clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. to reduce transients within the ad6643, minimize the length of the output data lines and loads that are placed on them. these transients can degrade converter dynamic performance. the lowest typical conversion rate of the ad6643 is 40 msps. at clock rates below 40 msps, dynamic performance can degrade. data clock output (dco) the ad6643 also provides data clock output (dco) intended for capturing the data in an external register. figure 2 shows a graphical timing diagram of the ad6643 output modes. table 11. output data format input (v) vin+ ? vin ? , input span = 1.75 v p-p (v) offset binary output mode twos complement mode (default) or vin+ ? vin? less than ?0.875 000 0000 0000 100 0000 0000 1 vin+ ? vin? ?0.875 000 0000 0000 100 0000 0000 0 vin+ ? vin? 0 100 0000 0000 000 0000 0000 0 vin+ ? vin? + 0.875 111 1111 1111 011 1111 1111 0 vin+ ? vin? greater than + 0.875 111 1111 1111 011 1111 1111 1
ad6643 rev. 0 | page 24 of 36 noise shaping requantizer (nsr) the ad6643 features a noise shaping requantizer (nsr) to allow higher than 11-bit snr to be maintained in a subset of the nyquist band. the harmonic performance of the receiver is unaffected by the nsr feature. when enabled, the nsr contributes an additional 0.6 db of loss to the input signal, such that a 0 dbfs input is reduced to ?0.6 dbfs at the output pins. the nsr feature can be independently controlled per channel via the spi. two different bandwidth modes are provided; the mode can be selected from the spi port. in each of the two modes, the center frequency of the band can be tuned such that ifs can be placed anywhere in the nyquist band. 22% bw mode (>40 mhz at 184.32 msps) the first bandwidth mode offers excellent noise performance over 22% of the adc sample rate (44% of the nyquist band) and can be centered by setting the nsr mode bits in the nsr control register (address 0x3c) to 000. in this mode, the useful frequency range can be set using the 6-bit tuning word in the nsr tuning register (address 0x3e). there are 57 possible tuning words (tw); each step is 0.5% of the adc sample rate. the following three equations describe the left band edge (f 0 ), the channel center (f center ), and the right band edge (f 1 ), respectively: f 0 = f adc .005 tw f center = f 0 + 0.11 f adc f 1 = f 0 + 0.22 f adc figure 39 to figure 41 show the typical spectrum that can be expected from the ad6643 in the 22% bw mode for three different tuning words. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090 frequency (hz) amplitude (dbfs) 09638-046 200msps 140.1mhz @ ?1.6dbfs snr = 73.6db (75.2dbfs) sfdr = 86dbc (in band) figure 39. 22% bw mode, tuning word = 13 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090 frequency (hz) amplitude (dbfs) 09638-047 200msps 140.1mhz @ ?1.6dbfs snr = 73.4db (75dbfs) sfdr = 86dbc (in band) figure 40. 22% bw mode, tuning word = 28 (f s /4 tuning) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090 frequency (hz) amplitude (dbfs) 09638-048 200msps 140.1mhz @ ?1.6dbfs snr = 73.5db (75.1dbfs) sfdr = 86dbc (in band) figure 41. 22% bw mode, tuning word = 41
ad6643 rev. 0 | page 25 of 36 33% bw mode (>60 mhz at 184.32 msps) the second bandwidth mode offers excellent noise performance over 33% of the adc sample rate (66% of the nyquist band) and can be centered by setting the nsr mode bits in the nsr control register (address 0x3c) to 001. in this mode, the useful frequency range can be set using the 6-bit tuning word in the nsr tuning register (address 0x3e). there are 34 possible tuning words (tw); each step is 0.5% of the adc sample rate. the following three equations describe the left band edge (f 0 ), the channel center (f center ), and the right band edge (f 1 ), respectively: f 0 = f adc .005 tw f center = f 0 + 0.165 f adc f 1 = f 0 + 0.33 f adc figure 42 to figure 44 show the typical spectrum that can be expected from the ad6643 in the 33% bw mode for three different tuning words. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090 frequency (hz) amplitude (dbfs) 09638-049 200msps 140.1mhz @ ?1.6dbfs snr = 71.3db (72.9dbfs) sfdr = 86dbc (in band) figure 42. 33% bw mode, tuning word = 5 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090 frequency (hz) amplitude (dbfs) 09638-050 200msps 140.1mhz @ ?1.6dbfs snr = 71.4db (73dbfs) sfdr = 86dbc (in band) figure 43. 33% bw mode, tuning word = 17 (f s /4 tuning) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090 frequency (hz) amplitude (dbfs) 09638-051 200msps 140.1mhz @ ?1.6dbfs snr = 71.2db (72.8dbfs) sfdr = 86dbc (in band) figure 44. 33% bw mode, tuning word = 27
ad6643 rev. 0 | page 26 of 36 channel/chip synchronization the ad6643 has a sync input that allows the user flexible synchronization options for synchronizing the internal blocks. the sync feature is useful for guaranteeing synchronized operation across multiple adcs. the input clock divider can be synchronized using the sync input. the divider can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence by setting the appropriate bits in register 0x3a. the sync input is internally synchronized to the sample clock. however, to ensure that there is no timing uncertainty between multiple parts, synchronize the sync input signal to the input clock signal. drive the sync input using a single-ended cmos type signal. using bit 1 in register 0x59, the sync input can be set to either level or edge sensitive mode. if the sync input is set to edge sensitive mode, use bit 0 of register 0x59 to determine whether the rising or falling edge is used.
ad6643 rev. 0 | page 27 of 36 serial port interface (spi) the ad6643 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the memory map section. for detailed operational information, see the an-877 application note, interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 12 ). the sclk (serial clock) pin is used to synchronize the read and write data presented from/to the adc. the sdio (serial data input/output) pin is a dual pur- pose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) pin is an active low control that enables or disables the read and write cycles. table 12. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data inp ut/output. a dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 45 and table 5 . other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 bit and the w1 bit. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the serial data input/output (sdio) pin to change direction from an input to an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/ output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb-first mode or in lsb-first mode. msb first is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note, interfacing to high speed adcs via spi, available at www.analog.com . hardware interface the pins described in table 12 comprise the physical interface between the users programming device and the serial port of the ad6643. both the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enou gh to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an-812 application note, microcon- troller-based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad6643 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are strapped to avdd or ground during device power-on, they are associated with a specific function. the digital outputs section describes the strappable functions supported on the ad6643.
ad6643 rev. 0 | page 28 of 36 spi accessible features table 13 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an-877 application note, interfacing to high speed adcs via spi (available at www.analog.com ). the ad6643 part- specific features are described in the memory map register description section. table 13. features accessible using the spi feature name description power mode allows the user to set either power-down mode or standby mode clock allows the user to access the dcs via the spi offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage digital processing allows the user to enable the synchroniza- tion features don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 09638-052 figure 45. serial port interface timing diagram
ad6643 rev. 0 | page 29 of 36 memory map reading the memory map register table each row in the memory map register table has eight bit locations. the memory map is roughly divided into four sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0x05 and address 0xff); the adc functions registers, including setup, control, and test (address 0x08 to address 0x25); and the digital feature control registers (address 0x3a to address 0x59). the memory map register table (see table 14 ) documents the default hexadecimal value for each hexadecimal address listed. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x14, the output mode register, has a hexadecimal default value of 0x05. this means that bit 0 = 1, and the remaining bits are 0s. this setting is the default output format value, which is twos complement. for more information on this function and others, see the an-877 application note, interfacing to high speed adcs via spi . this document details the functions controlled by register 0x00 to register 0x25. the remaining registers, from register 0x3a to register 0x59, are documented in the memory map register description section. open locations all address and bit locations that are not included in table 14 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default values after the ad6643 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 14 . logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x20, and address 0x3a to address 0x59 are shadowed. writes to these addresses do not affect device operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simultaneously when the transfer bit is set. the internal update takes place when the transfer bit is set, and then the bit autoclears. channel specific registers some channel setup functions, such as the signal monitor thresholds, can be programmed to a different value for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are desig- nated in table 1 4 as local. these local registers and bits can be accessed by setting the appropriate channel a or channel b bits in register 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, only channel a or channel b should be set to read one of the two registers. if both bits are set during an spi read cycle, the part returns the value for channel a. registers and bits designated as global in table 14 affect the entire device or the channel features where independent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits.
ad6643 rev. 0 | page 30 of 36 memory map register table all address and bit locations that are not included in table 14 are not currently supported for this device. table 14. memory map registers addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 0x00 spi port configuration (global) 1 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles are mirrored so lsb-first mode or msb-first mode registers correctly, regardless of shift mode 0x01 chip id (global) 8-bit chip id[7:0] (ad6643 = 0x84) (default) 0x84 read only 0x02 chip grade (global) open open speed grade id 10 = 200 msps open open open open speed grade id used to differentiate devices; read only channel index and transfer registers 0x05 channel index (global) open open open open open open adc b (default) adc a (default) 0x03 bits are set to determine which device on the chip receives the next write command; applies to local registers only 0xff transfer (global) open open open open open open open transfer 0x00 synchronously transfers data from the master shift register to the slave adc functions 0x08 power modes (local) open open external power- down pin function (local) 0 = power- down 1 = standby open open open internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = reserved 0x00 determines various generic modes of chip operation 0x09 global clock (global) open open open open open open open duty cycle stabilizer (default) 0x01 0x0b clock divide (global) open open input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 clock divide values other than 000 auto- matically cause the duty cycle stabilizer to become active
ad6643 rev. 0 | page 31 of 36 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x0d test mode (local) user test mode control 0 = continuous/ repeat pattern 1 = single pattern then zeros open reset pn long gen reset pn short gen output test mode 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn long sequence 0110 = pn short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output 0x00 when this register is set, the test data is placed on the output pins in place of normal data 0x0e bist enable (local) open open open open open reset bist sequence open bist enable 0x00 0x10 offset adjust (local) open open offset adjust in lsbs from +31 to ?32 (twos complement format) 0x00 0x14 output mode open open open output disable (local) open output invert (local) 1 = normal (default) 0 = inverted output format 00 = offset binary 01 = twos complement (default) 10 = gray code 11 = reserved (local) 0x05 configures the outputs and the format of the data 0x15 output adjust (global) open open open open lvds output drive current adjust 0000 = 3.72 ma output drive current 0001 = 3.5 ma output drive current (default) 0010 = 3.30 ma output drive current 0011 = 2.96 ma output drive current 0100 = 2.82 ma output drive current 0101 = 2.57 ma output drive current 0110 = 2.27 ma output drive current 0111 = 2.0 ma output drive current (reduced range) 1000 to 1111 = reserved 0x01 0x16 clock phase control (global) invert dco clock open open open open open open open 0x00 0x17 dco output delay (global) enable dco clock delay open open dco clock delay [delay = (3100 ps register value/31 +100)] 00000 = 100 ps 00001 = 200 ps 00010 = 300 ps 11110 = 3100 ps 11111 = 3200 ps 0x00 0x18 input span select (global) open open open full-scale input voltage selection 01111 = 2.087 v p-p 00001 = 1.772 v p-p 00000 = 1.75 v p-p (default) 11111 = 1.727 v p-p 10000 = 1.383 v p-p 0x00 full-scale input adjustment in 0.022 v steps 0x19 user test pattern 1 lsb (global) user test pattern 1[7:0] 0x00 0x1a user test pattern 1 msb (global) user test pattern 1[15:8] 0x00 0x1b user test pattern 2 lsb (global) user test pattern 2[7:0] 0x00 0x1c user test pattern 2 msb (global) user test pattern 2[15:8] 0x00
ad6643 rev. 0 | page 32 of 36 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x1d user test pattern 3 lsb (global) user test pattern 3[7:0] 0x00 0x1e user test pattern 3 msb (global) user test pattern 3[15:8] 0x00 0x1f user test pattern 4 lsb (global) user test pattern 4[7:0] 0x00 0x20 user test pattern 4 msb (global) user test pattern 4[15:8] 0x00 0x24 bist signature lsb (local) bist signature[7:0] 0x00 read only 0x25 bist signature msb (local) bist signature[15:8] 0x00 read only digital feature control registers 0x3a sync control (global) open open open open open open clock divider sync enable 0 = off 1 = on master sync enable 0 = off 1 = on 0x00 control register to synchronize the clock divider 0x3c nsr control (local) open open open open nsr mode 000 = 22% bw mode 001 = 33% bw mode nsr enable 0 = off 1 = on 0x00 noise shaping requantizer (nsr) controls 0x3e nsr tuning word (local) open open nsr tuning word see the noise shaping requantizer (nsr) section equations for the tuning word are dependent on the nsr mode 0x1c nsr frequency tuning word 0x59 sync pin control (local) open open open open open open sync pin sensitivity 0 = sync on high level 1 = sync on edge sync pin edge sensitivity 0 = sync on negative edge 1 = sync on positive edge 1 the channel index register at address 0x05 should be set to 0x03 (default) when writing to address 0x00. memory map register description for more information on functions controlled in register 0x00 to register 0x25, see the an-877 application note, interfacing to high speed adcs via spi , available at www.analog.com . sync control (register 0x3a) bits3reserved bit clock divider next sync only if the master sync enable buffer bit (address 0x3a, bit0) and the clock divider sync enable bit (address 0x3a, bit 1) are high, bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. the clock divider sync enable bit (address 0x3a, bit 1) resets after it syncs. bit 1clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is enabled when bit 1 is high and bit 0 is high. this is continuous sync mode. bit 0master sync buffer enable bit 0 must be set high to enable any of the sync functions. if the sync capability is not used this bit should remain low to conserve power.
ad6643 rev. 0 | page 33 of 36 nsr control (register 0x3c) bits[7:4]reserved bits[3:1]nsr mode bits[3:1] determine the bandwidth mode of the nsr. when bits[3:1] are set to 000, the nsr is configured for a 22% bw mode that provides enhanced snr performance over 22% of the sample rate. when bits[3:1] are set to 001, the nsr is con- figured for a 33% bw mode that provides enhanced snr performance over 33% of the sample rate. bit 0nsr enable the nsr is enabled when bit 0 is high and disabled when bit 0 is low. nsr tuning word (register 0x3e) bits[7:6]reserved bits[5:0]nsr tuning word the nsr tuning word sets the band edges of the nsr band. in 22% bw mode, there are 57 possible tuning words; in 33% bw mode, there are 34 possible tuning words. for either mode, each step represents 0.5% of the adc sample rate. for the equations that are used to calculate the tuning word based on the bw mode of operation, see the noise shaping requantizer (nsr) section. sync pin control (register 0x59) bits[7:2]reserved bit 1sync pin sensitivity if bit 1 is set to a 0, the sync input responds to a level. if this bit is set to high, the sync input responds to the edge (rising or falling) set in bit 0 of address 0x59. bit 0sync pin edge sensitivity if bit 1 is set high, setting bit 0 to a 0 causes the sync input to respond to a falling edge. likewise, if bit 0 is set to 1, the sync input responds to a rising edge.
ad6643 rev. 0 | page 34 of 36 applications information design guidelines before starting system level design and layout of the ad6643, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the ad6643, it is recommended that two separate 1.8 v supplies be used: one supply for analog (avdd) and a separate supply for the digital outputs (drvdd). the designer can employ several different decoupling capacitors to cover both high and low frequencies. locate these capacitors close to the point of entry at the pcb level and close to the pins of the device using minimal trace length. a single pcb ground plane should be sufficient when using the ad6643. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane on the pcb should mate to the ad6643 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. fill or plug these vias with nonconduc- tive epoxy. to maximize the coverage and adhesion between the adc and the pcb, overlay a silkscreen to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about packaging and pcb layout of chip scale packages, refer to the an-772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) . vcm decouple the vcm pin to ground with a 0.1 f capacitor, as shown in figure 29 . for optimal channel-to-channel isolation, a 33 resistor should be included between the ad6643 vcm pin and the channel a analog input network connection and between the ad6643 vcm pin and the channel b analog input network connection. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter per- formance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad6643 to keep these signals from transitioning at the converter inputs during critical sampling periods.
ad6643 rev. 0 | page 35 of 36 outline dimensions compliant to jedec standards mo-220-vmmd-4 091707-c 6.35 6.20 sq 6.05 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 46. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD6643BCPZ-200 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 ad6643bcpzrl7-200 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 ad6643-200ebz evaluation board with ad6643 1 z = rohs compliant part.
ad6643 rev. 0 | page 36 of 36 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09638-0-4/11(0)

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